Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
申请公布号
WO2016039893(A1)
申请公布日期
2016.03.17
申请号
WO2015US43835
申请日期
2015.08.05
申请人
INTEL CORPORATION
发明人
SRIVASTAVA, AMIT KUMAR;NS, KARTHIK;SHARMA, RAGHAVENDRA DEVAPPA;NEDALGI, DHARMARAY;BHILAWADI, PRASAD
