Error protection for a data bus

摘要

A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

主权项

1. A system for providing error detection or correction on a data bus, the system comprising:
one or more caches, wherein each cache is coupled to a central processing unit and to a hub by one or more data buses configured to transfer data between the one or more caches and the central processing unit; and a plurality of arrays, each array disposed on one of the one or more data buses, wherein each of the arrays comprises:
a plurality of storage cells disposed such that a direction of a data flow on the one or more data buses is orthogonal to an insensitive direction of the plurality of storage cells, wherein each of the plurality of storage cells comprise a gate conductor having a length and a width that is smaller than the length, and wherein the insensitive direction is a direction perpendicular to the width of the gate conductor; andan error control mechanism configured to enable detection of an error in the plurality of storage cells.