发明名称 |
Formation of silicide contacts in semiconductor devices |
摘要 |
Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions. |
申请公布号 |
US9129842(B2) |
申请公布日期 |
2015.09.08 |
申请号 |
US201414157927 |
申请日期 |
2014.01.17 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Tsai Yan-Ming;Lin Wei-Jung;Chen Fang-Cheng;Wu Chii-Ming |
分类号 |
H01L21/8238;H01L27/092;H01L21/324;H01L29/45;H01L29/16;H01L29/161;H01L21/285;H01L21/265 |
主分类号 |
H01L21/8238 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method comprising:
providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the n-type a-Si feature and the p-type a-SiGe feature; and performing a first annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si feature and a p-type a-SiGe feature, wherein during the first annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, a first silicide feature is formed in the nFET region, and a second silicide feature is formed in the pFET region. |
地址 |
Hsin-Chu TW |