发明名称 |
Transactional memory that supports a put with low priority ring command |
摘要 |
A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings). |
申请公布号 |
US8972630(B1) |
申请公布日期 |
2015.03.03 |
申请号 |
US201314037226 |
申请日期 |
2013.09.25 |
申请人 |
Netronome Systems, Incorporated |
发明人 |
Stark Gavin J. |
分类号 |
G06F3/00;G06F5/00;G06F9/46;G06F3/06 |
主分类号 |
G06F3/00 |
代理机构 |
Imperium Patent Works |
代理人 |
Imperium Patent Works ;Wallace T. Lester;Marrello Mark D. |
主权项 |
1. A method comprising:
(a) storing a ring of buffers in a memory unit of a transactional memory, wherein the ring of buffers includes a head buffer and a tail buffer; (b) maintaining a head pointer so that the head pointer points to the head buffer of the ring, and maintaining a tail pointer so that the tail pointer points to the tail buffer of the ring, wherein the head pointer and the tail pointer are maintained by a first stage of a pipeline of the transactional memory; (c) receiving a put into ring low priority command from a bus and onto the transactional memory; (d) in the first stage of the pipeline determining if the ring has an amount of unused buffer space; and (e) if the ring is determined in (d) to have the amount of unused buffer space then using the tail pointer to write a value into the tail buffer, wherein the writing of the value is performed by a stage of the pipeline other than the first stage, wherein the pipeline is clocked by a clock signal, and wherein the first stage processes a different command each cycle of the clock signal. |
地址 |
Santa Clara CA US |