| 发明名称 |
TEST BENCH HIERARCHY AND CONNECTIVITY IN A DEBUGGING ENVIRONMENT |
| 摘要 |
This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench. |
| 申请公布号 |
US2014331195(A1) |
申请公布日期 |
2014.11.06 |
| 申请号 |
US201414332157 |
申请日期 |
2014.07.15 |
| 申请人 |
Mentor Graphics Corporation |
发明人 |
Agarwala Badruddin;Parikh Tarak;Bhat Vivek;Joshi Neeraj |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
identifying, by a computing system, connectivity of library components in a test bench based, at least in part, on messages generated by connection calls during elaboration of the test bench; and interconnecting, by the computing system, symbol representations of the library components in a schematic representation of the test bench based, at least in part, on the identified connectivity of the library components. |
| 地址 |
Wilsonville OR US |
