发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME |
摘要 |
A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line. |
申请公布号 |
US2014204681(A1) |
申请公布日期 |
2014.07.24 |
申请号 |
US201213614486 |
申请日期 |
2012.09.13 |
申请人 |
Jo Seung Hee |
发明人 |
Jo Seung Hee |
分类号 |
G11C16/14 |
主分类号 |
G11C16/14 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor memory device, comprising:
a plurality of strings each configured to comprise a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line; andperipheral circuits configured to perform an operation of precharging a bit line so that a precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line. |
地址 |
Yongin-si KR |