Circuit providing load isolation and noise reduction

摘要

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

主权项

1. A memory module operable to communicate signals with a system memory controller, comprising:
a printed circuit board comprising at least one connector configured to be operatively coupled to the system memory controller; a plurality of memory devices on the printed circuit board; a circuit, comprising: a first set of ports comprising a plurality of bi-directional ports, each port of the first set of ports operatively coupled to at least one memory device of the plurality of memory devices; and a second set of ports comprising one or more bi-directional ports, each port of the second set of ports operatively coupled to the at least one connector; and a switching circuit configured to selectively and operatively couple one or more ports of the second set of ports to one or more selected ports of the first set of ports, the one or more selected ports being operatively coupled to one or more first memory devices that are being accessed by the system memory controller, wherein the switching circuit is further configured to reshape signals between the system memory controller and the one or more first memory devices so as to ameliorate signal deterioration due to transmission over lossy transmission lines having discontinuity regions between the system memory controller and the one or more first memory devices.