| 摘要 |
An integrated circuit 2 incorporates prefetch circuitry 12 for prefetching program instructions from a memory 6. The prefetch circuitry 12 includes a branch target address cache 28. The branch target address cache 28 stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory 6. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry 32 which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned. |
