发明名称 HYBRID GATE LAST INTEGRATION SCHEME FOR MULTI-LAYER HIGH-K GATE STACKS
摘要 A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film (104) at a first heat-treating temperature to diffuse a first chemical element from a first cap layer (108) into the first high-k film (104) in a device region (100a, 100b) to form a first modified high-k film (112, 1 13, 1 19). The method further includes a gate-last processing scheme to form recessed features (120, 122) defined by sidewall spacers (116, 140) in the device regions (100a, 100b) and depositing a second high-k film (124) in the recessed features (120, 122). Some embodiments include forming an oxygen scavenging layer (142, 152) on the first high-k film (104), where the heat-treating the first high-k film (104) scavenges oxygen from an interface layer (102, 103, 107) to eliminate or reduce the thickness of an interface layer (102, 103, 107).
申请公布号 WO2014062377(A2) 申请公布日期 2014.04.24
申请号 WO2013US62982 申请日期 2013.10.02
申请人 TOKYO ELECTRON LIMITED;TOKYO ELECTRON U.S. HOLDINGS, INC. 发明人 CLARK, ROBERT, D.
分类号 H01L21/8238;H01L21/28;H01L29/66 主分类号 H01L21/8238
代理机构 代理人
主权项
地址