发明名称 |
FREQUENCY DIVIDER AND PHASE-LOCKED LOOP INCLUDING THE SAME |
摘要 |
PURPOSE: A frequency demultiplier and a phase fixing loop including the same are provided to efficiently a demultiply ratio by using a demultiply control signal. CONSTITUTION: A first edge detecting unit(110) detects a first edge of an input signal based on a demultiply control signal to generate a first count signal. A second edge detecting unit(120) detects the first edge or a second edge of the input signal based on the demultiply control signal to generate a second count signal. A pulse triggered buffer unit(130) transits a logical level of an output node based on the first and the second count signals to generate an output signal. A mode selecting unit(140) sets a preset demultiply ratio as an odd demultiply ratio or an even demultiply ratio based on a selecting signal. |
申请公布号 |
KR20130002627(A) |
申请公布日期 |
2013.01.08 |
申请号 |
KR20110063687 |
申请日期 |
2011.06.29 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
YEO, HWAN SEOK;KIM, JI HYUN |
分类号 |
H03K23/00;H03L7/08 |
主分类号 |
H03K23/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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