| 摘要 |
A memory controller has write ports 110, 112 and read ports 130, 132. The ports are connected to different subsystems 160, 162 with a narrow data bus. The memory controller has a write arbiter 120 and a read arbiter 140 connected to memories 150, 152, 154 with a wider bus. Sequential writes to a data buffer in a write port by a subsystem are combined into a single write by the write arbiter to a memory. A single read by the read arbiter from the memory is split into sequential reads by a subsystem from a data buffer in the read port. An address buffer in the port is used to determine whether the accesses are sequential. The arbiter may schedule memory accesses from each of the ports in turn. The arbiter may write to the memory at the same frequency that the subsystems write to the data buffers. |
