| 摘要 |
<P>PROBLEM TO BE SOLVED: To inhibit occurrence of fluctuation and variation in transistor characteristics caused by polishing of a stress liner film formed to cover a gate electrode for applying stress to a channel region of a MOS transistor when an interlayer insulation film is polished and planarized by a CMP method. <P>SOLUTION: A semiconductor device manufacturing method comprises: forming only a first stress film (compression stress liner film) 16 on a gate electrode (a multilayer film of a silicon film 14 and a metal silicide film 15) on a first active region (e.g., P channel transistor formation region); forming only a second stress film (tensile stress liner film) 18 on a gate electrode on a second active region (e.g., N channel transistor region); forming, on the other hand, a multilayer film of the first and the second stress films 16, 18 on a gate electrode on an element isolation 10; and stopping polishing of an interlayer insulation film 20 by a CMP method after exposure of the second stress film 18 on the element isolation 10. <P>COPYRIGHT: (C)2013,JPO&INPIT |
