发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL (Phase Locked Loop) circuit which obtains a VCO (Voltage Controlled Oscillator) output having satisfactory spurious output characteristics with respect to all channels and which has suppressed fluctuation in the characteristics due to a temperature change.SOLUTION: In the PLL circuit, a control circuit 3 includes a temperature sensor 31 and a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a voltage controlled oscillator for each channel number in accordance with a temperature are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS (Direct Digital Synthesizer) circuit (reference frequency generation circuit) 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency corresponding to the value.
申请公布号 JP2011019208(A) 申请公布日期 2011.01.27
申请号 JP20100081506 申请日期 2010.03.31
申请人 NIPPON DEMPA KOGYO CO LTD 发明人 KIMURA HIROKI
分类号 H03L7/183 主分类号 H03L7/183
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