发明名称 INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
摘要 An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.
申请公布号 US2010091595(A1) 申请公布日期 2010.04.15
申请号 US20080251010 申请日期 2008.10.14
申请人 QIMONDA NORTH AMERICA CORP. 发明人 FEKIH-ROMDHANE KHALED
分类号 G11C29/00;G11C8/18 主分类号 G11C29/00
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