发明名称 Latch circuit
摘要 A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
申请公布号 US2007268054(A1) 申请公布日期 2007.11.22
申请号 US20060635517 申请日期 2006.12.08
申请人 FUJITSU LIMITED 发明人 UEMURA TAIKI;TOSAKA YOSHIHARU
分类号 H03K3/289 主分类号 H03K3/289
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