发明名称 ELEMENT FOR RESISTANCE EVALUATION AND PACKAGE PROCESS EVALUATION METHOD OF SEMICONDUCTOR DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a method which evaluates the physical resistance in a package process with high precision and high sensitivity. <P>SOLUTION: The element for evaluation of the physical resistance in the package process of a semiconductor device is equipped with a substrate 1, an interconnection film 3 prepared on the substrate 1, and an insulation film 2 whose elastic modulus is 15 GPa or less prepared in the lower layer and/or the upper layer of the interconnection film 3. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007184506(A) 申请公布日期 2007.07.19
申请号 JP20060003041 申请日期 2006.01.10
申请人 CONSORTIUM FOR ADVANCED SEMICONDUCTOR MATERIALS &RELATED TECHNOLOGIES 发明人 MINAMIHASHI KATSUYA;IZUMITANI SEIJI
分类号 H01L21/66;H01L21/768;H01L23/522 主分类号 H01L21/66
代理机构 代理人
主权项
地址