发明名称 Trench isolation methods of semiconductor device
摘要 In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.
申请公布号 US2006240636(A1) 申请公布日期 2006.10.26
申请号 US20060358454 申请日期 2006.02.21
申请人 RYU HYUK-JU;SHIN HEON-JONG;KANG HEE-SUNG;RYOU CHOONG-RYUL;JUNG MU-KYENG;KIM KYUNG-SOO 发明人 RYU HYUK-JU;SHIN HEON-JONG;KANG HEE-SUNG;RYOU CHOONG-RYUL;JUNG MU-KYENG;KIM KYUNG-SOO
分类号 H01L21/76 主分类号 H01L21/76
代理机构 代理人
主权项
地址