| 摘要 |
There is provided at least one processor block including a plurality of load store interfaces ( 801, 804 ), a plurality of memory banks ( 821 ), an input/output port having at least one of an input port ( 850 ) and an output port ( 860 ), and a crossbar switch ( 810 ), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.
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