| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce an area occupied by a direct peripheral circuit (sense amplifier, word shunt, etc.) in a large capacity DRAM having a memory cell with a COB (Capacitor Over Bitline) structure. <P>SOLUTION: By electrically connecting an n-channel type MISFETQs in the direct peripheral circuit arranged in close to a memory array and a common source line PN<SB>1</SB>via a pad layer 16 composed of the same conductive film as that of a storage electrode 15 of the memory cell, the aspect ratio of a contact hole 22 formed at the upper part of the pad layer 16 is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
