发明名称 |
System and method for topology selection to minimize leakage power during synthesis |
摘要 |
A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.
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申请公布号 |
US2005125761(A1) |
申请公布日期 |
2005.06.09 |
申请号 |
US20030731840 |
申请日期 |
2003.12.09 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JACOBSON HANS M.;KUDVA PRABHAKAR N.;SIGAL LEON J. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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