FIFO MEMORY CONTROL SYSTEM AND INFORMATION DATA PROCESSOR

摘要

PROBLEM TO BE SOLVED: To reduce the load of the FIFO memory access of a CPU. SOLUTION: This FIFO memory control system of an information data processor is configured to use an FIFO memory as the buffer memory for transmission/reception of the information data processor constituted of a CPU and a communication LSI, and to execute especially two or more system communication by one CPU. This FIFO memory control system is provided with a congestion monitor control circuit for controlling the writing of data in an FIFO memory reservation area when it is possible to write data in the FIFO memory reservation area as countermeasures to the overflow of the FIFO memory. COPYRIGHT: (C)2005,JPO&NCIPI