发明名称 Checkerboard buffer using more than two memory devices
摘要 Methods and apparatus for storing and retrieving data in parallel but in different orders, using three or more memory devices. In one implementation, data for pixels is stored according to a checkered pattern, sequentially among memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least three memory devices each having memory locations, where data is stored in parallel to and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, the second data switch controls providing data to the data destination according to the second order.
申请公布号 US6768490(B2) 申请公布日期 2004.07.27
申请号 US20020077636 申请日期 2002.02.15
申请人 SONY CORPORATION;SONY ELECTRONICS INC. 发明人 CHAMPION MARK;DOCKTER BRIAN
分类号 G06T1/60;G09G3/00;G09G3/34;G09G5/39;G09G5/391;G09G5/393;G09G5/395;G09G5/399;G11C7/10;H04N5/14;H04N5/44;H04N5/46;H04N5/74;H04N7/01;(IPC1-7):G09G5/36 主分类号 G06T1/60
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