| 摘要 |
PROBLEM TO BE SOLVED: To provide a pass transistor logic circuit capable of designing an SPL circuit operable with a manual minimized layout correction by realizing the smaller current consumption and area than in a CMOS logic circuit. SOLUTION: An initial value is given to all nodes of a BDD including an intermediate node and a terminal end node, a value obtained by subtracting 1 from the value of a node is divided by the maximum output signal number, and 1 is added to the resulting quotient. The respective values of two slave nodes are incremented by the resulting value, and when the node is mapped by a pass transistor, equivalent nodes are copied by the number of quotient, and an output signal is divided so as to have the maximum output signal number or less. COPYRIGHT: (C)2004,JPO
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