发明名称 CHIP MOUNTING METHOD AND SYSTEM THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a method for manufacturing a chip capable of simply and promptly inspecting qualities of a plurality of integrated circuits to manufacture a non-defective circuit chip. SOLUTION: A plurality of integrated circuits and common wires are formed on a circuit substrate, and in a state that an electrode pad is not connected to the common wire, the plurality of integrated circuits are individually inspected. In the integrated circuit determined as non-defective, the electrode pad is connected to the common wire the uniformly load stress, and after the completion thereof, the electrode pad is disconnected from the common wire to individually inspect the integrated circuits. The stress can be loaded to the plurality of integrated circuits at one time by utilizing the common wire, and nevertheless, when the integrated circuit is inspected as a connection with the common wire is disconnected, the integrated circuits can individually be inspected. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003209147(A) 申请公布日期 2003.07.25
申请号 JP20020004504 申请日期 2002.01.11
申请人 NEC MICROSYSTEMS LTD 发明人 KUMAMOTO TAKEYA
分类号 G01R31/30;G01R31/28;H01L21/66;H01L23/544;(IPC1-7):H01L21/66 主分类号 G01R31/30
代理机构 代理人
主权项
地址