发明名称 |
Multiple oxide thicknesses for merged memory and logic applications |
摘要 |
Methods are provided for fabricating multiple oxide thicknesses on a single silicon wafer. Methods are provided to form multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. These methods can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Methods for forming a semiconductor device include forming a top layer of SiO2 on a top surface of a silicon wafer. A trench layer of SiO2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO2 are such that a thickness of the top layer is different from a thickness of the trench layer.
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申请公布号 |
US2002127884(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
US20020140297 |
申请日期 |
2002.05.06 |
申请人 |
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发明人 |
NOBLE WENDELL P.;FORBES LEONARD |
分类号 |
H01L21/316;H01L21/8234;H01L21/8242;H01L21/8247;H01L27/115;(IPC1-7):H01L21/31 |
主分类号 |
H01L21/316 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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