| 摘要 |
PROBLEM TO BE SOLVED: To suppress a clock skew and to execute a high speed operation by receiving a current level, amplifying it to a voltage level regulated by an output clock and executing conversion. SOLUTION: A clock distribution circuit 21 converts the voltage change of an input clock signal CK into the current level change of two sense lines L1 and L2 with a clock driving circuit D. The current level difference is converted into a potential difference with the sense amplifiers of clock reception circuits R1-Rn. A voltage differential amplifier and a waveform shaping circuit execute amplification at high speed and output it as the output clock signals CK1-Ckn. The transmission delay time of the clock signal is reduced and the clock skew can be reduced without being affected by the load capacity of sense lines L1 and L2 and even if the wiring lengths of sense lines L1 and L2 to the respective clock reception circuits R1-Rn become mutually different. |
