| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL, which can suppress the generation of pseudo phase error signal and eliminates a problem such as inverse phase synchronism, by generating a zero discriminate signal by detecting the zero level of level discriminate signal outputted by a level discriminator, and inhibiting a phase error output in the case of pseudo signal generation while using the zero discriminate signal. SOLUTION: A level discriminator 1 discriminates the signal level of sampling reproduced signal Vk and outputs a level discriminate signal QVk. In the case of level discriminate signal QVk=0, a zero discriminate signal ZK=1 by the zero discriminator 7, in the case of QVk=1 or QVk=-1, Zk=0 is outputted and a zero discriminate signal Zk-1 delayed for one sample clock through a 1T delayer 8 is outputted. The zero discriminate signals ZK and ZK-1 are respectively inputted to three-input multipliers 5 and 4. Thus, the generation of phase error signal locked with the inverse phase of conventional phase error signal waveform can be suppressed. |
