发明名称 |
METHOD FOR MANUFACTURING CHIP SIZE PACKAGE IMPROVING SOLDER JOINT CHARACTERISTIC |
摘要 |
PURPOSE: A method for manufacturing a chip size package(CSP) is provided to reduce manufacturing cost without performing an under bump metal(UBM) process, and to prevent reliability of a solder joint part from being decreased by thermal stress by improving the solder joint characteristic. CONSTITUTION: A convexo-concave structure is formed on a chip pad(2) including a plurality of chip pads. A photosensitive material is coated on a chip(1) having the convexo-concave structure. The surface of the chip coated with the photosensitive material is polished to make the photosensitive material and an end portion of the convexo-concave structure become horizontal. Masks are disposed on the surface-polished chip and light is irradiated. The photosensitive material is developed to expose the convexo-concave structure formed on the chip pad. Flux is printed on the chip pad opened by exposing the convexo-concave structure. A solder ball(8) is mounted on the flux and reflowed to adhere the solder ball to an upper surface of the chip pad. |
申请公布号 |
KR20010028754(A) |
申请公布日期 |
2001.04.06 |
申请号 |
KR19990041158 |
申请日期 |
1999.09.22 |
申请人 |
HYUNDAI MICRO ELECTRONICS CO., LTD. |
发明人 |
CHO, JAE WON |
分类号 |
H01L21/60;(IPC1-7):H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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