| 摘要 |
An architecture for video decompressor to efficiently access synchronously memory includes a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of scan lines and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N+0)-th and (4N+1)-th scan lines, and the B-bank is sequentially stored with the (4N+2)-th and (4N+3)-th scan lines, where N is a non-negative integer, so as to always perform memory operations by alternately accessing the A-bank and B-bank. |
