Cache DataRam of one port ram cell structure

摘要

The present invention provides a cache DataRam with one port ram cell configuration which improves the implemented area efficiency, performance and power savings. The cache DataRam of superscalar processor having multiple pipelines includes: a plurality of banks for multiple data access requests from the multiple pipelines, the plurality of banks forming into one port ram cell structure; a bank selection signal generation circuitry for generating a bank selection signal representing on which bank a data requested by the pipeline is located in response to address signals and control signals inputted from each pipeline for data access; a address selector for selecting an index address out of plurality of index addresses from the pipelines and outputting the selected index address as a valid pipeline index address in response to the bank selection signal; a decoder for decoding the valid pipeline index address for each bank; and a hitway selector for selecting a hitway signal out of hitway signals of the pipelines and outputting the selected hitway signal as a valid pipeline hitway signal, the hitway signals being generated by tag block for the each bank in response to the bank selection signal.