发明名称 |
Semiconductor circuit device with reduced power consumption in slow operation mode. |
摘要 |
In a DRAM employing a shared sense amplifier method, a bit line select signal falls to the level of ground potential after a potential difference is generated between a pair of bit lines and sense nodes in response to activation of a word line in a self refresh mode for disconnecting the bit line pair in a memory block including the activated word line from a sense amplifier. When the potentials of the sense nodes are amplified by the sense amplifier, the disconnected bit line pair is connected again to the sense amplifier.
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申请公布号 |
US6058061(A) |
申请公布日期 |
2000.05.02 |
申请号 |
US19980110689 |
申请日期 |
1998.07.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OOISHI, TSUKASA |
分类号 |
G11C11/403;G11C7/06;G11C7/10;G11C11/401;G11C11/406;G11C11/4074;G11C11/409;G11C11/4091;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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