| 摘要 |
PROBLEM TO BE SOLVED: To continuously supply a stable internal clock signal to an internal circuit by providing a second switch circuit for selecting a clock enable signal in a first state and for selecting the output signal of a first latch circuit in a second state for supplying to a second latch circuit. SOLUTION: A clock enable signal CKE is inputted to the input circuit of an input buffer 10. When the clock enable signal CKE is set to an L level, the output of clock signals CLK1 and CLK2 is stopped and the input buffer 10 is shifted to a power-down mode. When the clock enable signal CKE is set to an H level, an internal clock signal I-CLK is stopped and outputted at the same timing as non-overflow when shifting to the power mode or returning to a normal mode even when a DLL circuit 20 overflows, thus preventing malfunction where a command latch circuit 21 cannot fetch a command input signal COM-IN such as a cell refresh command. |
