Semiconductor integrated circuit device including a plurality of divided sub-bit lines

摘要

A nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines includes a plurality of sub-bit lines. Each sub-bit line is connected to an appropriate main bit line through a first and a second selection MISFET. The first selection MISFET has a thin gate insulating film and is used for read operations only. The second MISFET has a thick gate insulating film and is used at least for write operations. In a write operation, the first selection MISFET has its drain or its gate supplied with a predetermined bias voltage so that the gate insulating film of the transistor will not be subjected to a voltage defeating the dielectric strength of the film.