| 摘要 |
<p>The data processor contains a memory and a data prefetch unit. The data prefetch unit contains a respective FIFO queue for storing prefetched data from each of a number of address streams respectively. The data prefetch unit uses programmable information to generate addresses from a plurality of address streams and prefetches data from addresses successively addressed by a present address for the data stream in response to progress of execution of a program by the processor. The processor has an instruction which causes the data prefetch unit to extract an oldest data from the FIFO queue for an address stream and which causes the data processor to use the oldest data in the manner of operand data of the instruction.</p> |
