发明名称 DISCRETE PHASE LOCKED LOOP
摘要 A discrete phase locked loop and method for supporting global synchronization of data communications in a mobile communications system is disclosed. In order to provide for air frame synchronization, air frame data clocks and a synchronization signal must be phase locked to a global time reference signal. This is accomplished through a fully discrete phase locked loop in ASIC on software wherein a state machine is clocked by a high frequency, high accuracy, fixed frequency source already available in the radio terminal equipment. The state machine generates the required air frame data clocks and synchronization signals by completing a counter cycle. At regular intervals, this counter can skip, or double step, for one count to adjust the output phase closer to the phase of the reference signal. The interval for which this correction is maintained is settable by an interval counter. This implementation mimics an elliptic low pass filter.
申请公布号 CA2240429(A1) 申请公布日期 1997.06.26
申请号 CA19962240429 申请日期 1996.12.13
申请人 TELEFONAKTIEBOLAGET LM ERICSSON 发明人 JANSSON, JOHAN
分类号 H03L7/099;H04B7/26;(IPC1-7):H03L7/099;H04Q7/30 主分类号 H03L7/099
代理机构 代理人
主权项
地址