| 摘要 |
PROBLEM TO BE SOLVED: To reduce a synchronization acquisition time by using a matched filter so as to detect a reception signal and a correlation signal and using the correlation signal so as to generate a clock phase switching timing for demodulating the reception signal. SOLUTION: A control circuit 101 receiving a load timing signal compares a peak signal of a matched filter 109 with an output of a frequency divider circuit 107. When both the signals reach an L level, the control circuit 101 provides a switching signal to throw a switch 108 to the position through which the peak signal of the filter 109 is given to a phase comparator 104. The throwing state of the switch 108 is maintained till the absence of a reception signal is detected by monitoring the peak signal of the filter 109. Furthermore, the comparator 1-4 receiving the peak signal of the filter 109 compares a phase of a leading edge of an output of a frequency divider circuit 102 with a phase of a leading edge of the peak signal of the filter 109 and clock phase locking is conducted from an approximated phase by changing a control voltage of a VCO 105. |
