| 摘要 |
In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter (7) to a memory circuit having the spare address and the normal address, before the counter (7) outputs an address to the memory circuit, the spare/normal discriminating circuit (5) acquires previously the address outputted from the counter (7) and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits (3 and 4) switch the address to be applied from the select circuits (3 and 4) to the memory circuit from the normal address to the spare address or vice versa. <IMAGE> <IMAGE> |
