| 摘要 |
<p>PURPOSE: To enable high speed random reading without increasing an area by constituting a sub-array with two memory units in which magnitude relation of threshold values of selecting MOS transistors (STD), (STS), allowing a NAND cell to conduct to a bit line and a source line respectively, is different. CONSTITUTION: A NAND cell C00 connected in series to a memory cell unit 1 is conducted to a bit line the inverse of BLO and a source line through STD10 , STS10 . As for a memory cell unit 2, conduction is performed through STD00 , STS00 in the same way. A threshold value of the STD10 is larger than a threshold value of STS10 , a threshold value of the STS00 is larger than a threshold value of STD00 , a memory sub-array is constituted of plural memory units 1, 2 in which magnitude relation of threshold values is different, and a folded bit line system can be realized. Thereby, high speed random read can be performed without increasing a chip area.</p> |
