SYNCHRONIZING SIGNAL GENERATING CIRCUIT AND A/D CONVERTER USING THE CIRCUIT

摘要

PURPOSE:To provide the synchronizing signal generating circuit frequency- dividing a master clock to generate two independent new clock systems and the A/D converter without the effect of feed-through. CONSTITUTION:The synchronizing signal generating circuit is provided with a 1st frequency divider means 2 generating a clock (WCLK) with a large frequency division ratio and a 2nd frequency divider means 3 receiving the clock from the 1st frequency divider and generating a clock (CCLK) with a small frequency division ratio used to reset the count of the frequency division at a drive edge of the said clock. The A/D converter employs the synchronizing signal generating circuit and drives a sample-and-hold circuit with an output clock of the 1st frequency divider means 2 and the output clock of the 2nd frequency divider means 3 drives the A/D converter circuit. As a result, since a 2nd clock whose phase is shifted periodically for every occasion in the A/D conversion cycle is not produced, the effect of feed-through due to it is reduced.