| 摘要 |
A decoder for improving the reliability of synchronization pattern detection. The decoder includes a synchronization circuit for detecting a synchronization pattern from LPP data and wobble data. A first frame counter is reset when a synchronization detection circuit detects the synchronization pattern of a first sector and counts the number of frames of data until the synchronization pattern of the next sector is detected. A comparison circuit compares a count value of the first frame counter with a first reference value, which corresponds to the number of frames for one sector. A determination circuit determines whether or not the detected synchronization pattern is proper based on the comparison result of the comparison circuit.
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