Method of manufacturing semiconductor device

摘要

Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.

主权项

1. A semiconductor device, comprising:
a base material having a surface, a wiring formed on the surface, and a solder resist film covering the wiring; a first chip group including a first semiconductor chip and a second semiconductor chip, and mounted on a surface of the solder resist film; a second chip group including a first semiconductor chip, a second semiconductor chip and a third semiconductor chip, and mounted on the first chip group; a first wire group including a plurality of first wires and a plurality of second wires, and connected with the first chip group; a second wire group including a plurality of first wires, a plurality of second wires and a plurality of third wires, and connected with the second chip group; and a sealing body sealing the first chip group, the second chip group, the first wire group and the second wire group, wherein the sealing body has a first side surface and a second side surface opposite to the first side surface, wherein the first semiconductor chip of the first chip group has a side surface along which a plurality of pads connected with the plurality of first wires of the first wire group are arranged, and facing the first side surface of the sealing body, wherein the second semiconductor chip of the first chip group has a side surface along which a plurality of pads connected with the plurality of second wires of the first wire group are arranged, and facing the first side surface of the sealing body, wherein the first semiconductor chip of the second chip group has a side surface along which a plurality of pads connected with the plurality of first wires of the second wire group are arranged, and facing the second side surface of the sealing body, wherein the second semiconductor chip of the second chip group has a side surface along which a plurality of pads connected with the plurality of second wires of the second wire group are arranged, and facing the second side surface of the sealing body, wherein the third semiconductor chip of the second chip group has a side surface along which a plurality of pads connected with the plurality of third wires of the second wire group are arranged, and facing the second side surface of the sealing body, wherein the first semiconductor chip of the first chip group is a lowermost chip, wherein the first semiconductor chip of the second chip group is a lowermost chip of the second chip group, wherein the third semiconductor chip of the second chip group is an uppermost chip, wherein each of the third semiconductor chip of the second chip group, the first semiconductor chip of the second chip group and the first semiconductor chip of the first chip group has greater thickness than each of the second semiconductor chip of the first chip group and the second semiconductor chip of the second chip group, and wherein the third semiconductor chip of the second chip group, the first semiconductor chip of the second chip group and the first semiconductor chip of the first chip group have the same thickness.