| 摘要 |
PURPOSE:To improve the precision of input data by switching plural analog signals at a timing shifted from the sampling timing of an A/D converter. CONSTITUTION:At the time of data input, a control means outputs a start pulse PT whose pulse width is longer than one cycle of a sampling clock SP, and one clock SP' appears in a signal S1 by an AND circuit 11. An FF 13 is set by the rise of the signal S1, and a signal S3 rises, and an AND circuit 10 is made operatable. Hereafter, a sampling clock SPd having the same waveform as the clock SP is outputted from the circuit 10. Then, an A/D con verter 2 is operated to sample the input process signal PS1 by the rise of the signal SPd, and a digital signal Ds is outputted to a PID controller 4. The signal PS1 is successively switched to signals PS2 and PSd1 by a switching signal SL outputted from an FF 18 by switching signals SL12 and SL21 whose cycle is longer than that of the signal SP, thus preventing the degradation of the precision of input data to a PID controller. |
