| 发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT LATCH-UP PREVENTING APPARATUS |
| 摘要 |
This invention discloses a semiconductor integrated circuit latch-up preventing apparatus. Impurity diffusion regions (9) are formed along uppermost and lowermost cell arrays (11-1, 11-n) in an internal element region (2), and power supply lines (12) are formed on the impurity diffusion regions (9). |
| 申请公布号 |
EP0278065(A3) |
申请公布日期 |
1990.05.09 |
| 申请号 |
EP19870116426 |
申请日期 |
1987.11.06 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MORIMOTO, TOSHIKI C/O PATENT DIVISION K.K. TOSHIBA;WATANABE, SEIJI C/O PATENT DIVISION K.K. TOSHIBA;TANAKA, YUTAKA C/O PATENT DIVISION K.K. TOSHIBA |
| 分类号 |
H01L21/82;H01L21/3205;H01L21/822;H01L23/52;H01L23/528;H01L27/04;H01L27/092;H01L27/118;(IPC1-7):H01L27/08 |
主分类号 |
H01L21/82 |
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