Electrical circuit for interfacing high frequency signals to the logic levels of any logic family having a switching voltage at the mean of the 0 and 1 voltages

摘要

An interface circuit, particularly for use between a high frequency sine wave and ECL (emitter-coupled logic) logic levels, which has an almost resistive input inpedance. The circuit may comprise an ECL OR/NOR gate (3) with the complementary outputs thereof having respective feedback paths (R2,R1; R3,R1). The high frequency sine wave is supplied via a coaxial cable (4) which is terminated via resistor R1. The feedback resistors R2 and R3 are of the same value. The mark-to-space ratio at the gate outputs is substantially maintained at 50/50. The gate may be AND/NAND rather than OR/NOR. The interface circuit is applicable to any logic family having a switching voltage at the mean of the "0" and "1" voltages.