| 摘要 |
PURPOSE:To facilitate submicron implementation of a gate length and the formation of a source electrode at the back surface of a substrate, by using the heterojunction plane between a high resistance semiconductor layer and a low resistance semiconductor layer as a gate, and using both upper and lower end parts of a two-dimensional gas channel (2DEG) layer, which is formed on the side surface of the high resistance semiconductor layer as a source and a drain, thereby reducing parasitic resistance. CONSTITUTION:Etching is performed in a fault shape, and a source, a gate and a drain are formed on the fault surface. The heterojunction plane between a second low resistance semiconductor layer 15 and a high resistance semiconductor layer 11 functions as a gate. The length of a gate is determined by the thickness of the high resistance semiconductor layer 11 and the slant angle of a side wall 14. Upper and lower end parts 21 and 22 on a 2DEG layer substantially function as a source and a drain. For example, the drain is positioned at the upper end part 22, and the source is positioned at the lower end part 21. Then this structure is suitable for a high frequency element. When, the source is positioned at the upper side and the drain is positioned at the lower side, the structure is suitable for a large-output element. |
