发明名称 |
AUTOMATIC SYNTHESIS SYSTEM FOR PROTOCOL |
摘要 |
PURPOSE:To give a specification without contradiction of logic to an incomplete protocol by dividing a state transition at every process and synthesizing the existing state transition to a state transition generated additionally at every process when the state transition of the opposite process is deficient. CONSTITUTION:An incomplete protocol specification is stored in a memory 1, an initial setting block 2 accesses the memory 1 to obtain an incomplete state transition diagram. A D conversion block 3 accesses the memory 1 to divide the state transition diagram of the process 1 into a part transmitting/ receiving a signal with a process 2 and a part transmitting/receiving a signal with a process 3, and the divided parts are stored in the memory 4. A T conversion block 5 accesses a memory 4 to produce the state transition deficient in the opposite process at every channel and it is stored in a memory 6. A C conversion block 7 accesses the memory 6 to synthesize the state transition diagram produced at every channel and the complete state transition diagram of each process is obtained and stored in a memory 8.
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申请公布号 |
JPS61200740(A) |
申请公布日期 |
1986.09.05 |
申请号 |
JP19850041185 |
申请日期 |
1985.03.04 |
申请人 |
KOKUSAI DENSHIN DENWA CO LTD <KDD> |
发明人 |
TSUNODA YOSHIAKI;WAKAHARA YASUSHI;NORIKOSHI MASAMITSU |
分类号 |
G06F11/00;G06F13/00;H04L13/00;H04L29/06 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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