发明名称 PARALLEL OPERATION PROCESSING DEVICE
摘要 PURPOSE:To perform high-speed processing with a small-sized and low-cost device by adding an execution control circuit to each arithmetic circuit and providing each arithmetic circuit with the function which stops the arithmetic circuit itself in accordance with decision result, the function which restores the arithmetic circuit from the stop state, etc. CONSTITUTION:Execution control circuits 4a-4n evaluate contents of control flags 16a-16n in accordance with an execution instruction 14 from an execution instruction generating circuit 1 and control arithmetic circuits 3a-3n by control signals 17a-17n. That is, each arithmetic circuit is provided with the function which stops the arithmetic circuit itself in accordance with the decision result, the function which restores the arithmetic circuit from the stop state, the function which inverts the stop/execution state of the arithmetic circuit, etc. at least. Thus, parallel operations can be performed even if branch processings exist in a program. Stack circuits where execution/stop states of arithmetic circuits are provided besides these functions, and control is executed in accordance with contents of stack circuits, thereby performing high-speed processings with the small-sized and low-cost device.
申请公布号 JPS60134957(A) 申请公布日期 1985.07.18
申请号 JP19830241993 申请日期 1983.12.23
申请人 HITACHI SEISAKUSHO KK 发明人 YODA HARUO
分类号 G06F15/80;G06F15/16;G06T1/00;G06T1/20 主分类号 G06F15/80
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