发明名称 MANUFACTURE OF SEMICONDUCTOR SUBSTRATE
摘要 PURPOSE:To reduce the irregularity of element characteristics of an IC by a method wherein the resistance value distribution of a semiconductor substrate is compensated by performing an ion implanting method. CONSTITUTION:The distribution of resistance value of the silicon wafer of P type (100) face of 10OMEGA.cm when impurities such as boron and phosphorus are doped, which is the distribution of resistance value caused by the so-called striation, is present on a silicon substrate as indicated by a solid line in the diagram. The irregularity of the threshold voltage VTH caused by the irregularity of said resistance value is approximately 0.1V. For the purpose of compensating such irregularity as above-mentioned by performing an ion implanting method, the beam scanning voltage of an ion implanting machine is adjusted, and high density impurities are doped on the part where impurity density is low, thereby enabling to obtain a uniform distribution of resistance value. To be more precise, the curved line 4 shown by a broken line in the diagram indicates the resistance value distribution of the impurities doped by performing an ion implanting method, and when this is added to the intrinsic resistance value distribution of the wafer, a uniform resistance value distribution can be obtained as indicated by the one-dot chain line 5 in the diagram.
申请公布号 JPS6038815(A) 申请公布日期 1985.02.28
申请号 JP19830146391 申请日期 1983.08.12
申请人 HITACHI SEISAKUSHO KK 发明人 WADA YASUO;HASHIMOTO TETSUKAZU
分类号 H01L21/265;(IPC1-7):H01L21/265 主分类号 H01L21/265
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