| 摘要 |
PURPOSE:To obtain a stable clock signal in a capture range by dividing the frequency of the output of a variable frequency oscillating circuit by N to generate a reference frequency approximating 1/N of the bit frequency of an input signal and detecting a phase difference between both signals and controlling said oscillating circuit by the detection output. CONSTITUTION:If it is detected that a clock signal is not synchronized with a digital signal A to close a switch 6, the phase of an output frequency-divided clock signal E of a frequency divider 3 and that of a reference clock signal F are compared with each other. At this time, frequencies fE and fF are 1/N of fc and fb, and the frequency diference and the phase difference between fc and fb are 1/N, and the signal E is synchronized with the signal F even in case of a slight deviation between fc and fb because signals E and F are inverted at intervals of a half period. Consequently, a clock signal c is synchronized with the digital signal A easily when the switch 6 is opened. Thus, an integer N and the frequency fF are so selected that N.fFapprox.=fb is true, and a phase difference G between signals F and E is applied to an oscillating circuit 2 to synchronize them, and thereafter, the signal C is synchronized with the signal A. An LPF7 raises the gain of a phase synchronizing loop to extend the capture range. |
