| 摘要 |
PURPOSE:To reduce the power consumption of the entitled circuit substantially by controlling the input of a clock at least by an output of the shift register of >=2 steps before and that of the shift register of >=1 step after. CONSTITUTION:When a target pulse arrives the shift register (SR) 3m-2 of 2 steps before and an output Q is generated, Q' is turned to the low level and therefore the output of an NAND circuit 5m is reversed. An NAND circuit 7m becomes equivalent to an inverter connected to a clock line and the said pulse is applied to the NAND circuit 7m as a clock bar. When the target pulse is shifted to an SR 3m-1 and inputted to an SR 3m+1, the output Q' is turned to the low level and therefore a flip-flop circuit consisting of the NAND circuits 5m, 6m is reset and returned to the original status. The circuit 7m is closed and an SR 1m stops again. Thus, each SR operates precisely by 3 periods of a clock pulse. |
